1. Field of the Invention
This invention relates to the field of semiconductor processing and, more particularly, to an improved method of planarizing a shallow trench dielectric using a combination of a spin-on deposited flowable oxide and a chemical-mechanical polish.
2. Description of Relevant Art
The fabrication of an integrated circuit involves placing numerous devices on a single semiconductor substrate. Isolation structures are needed to electrically isolate one device from another. Isolation structures define the field regions of the semiconductor substrate and the device areas define the active regions. The devices are interconnected with conducting lines running over the isolation structures.
A popular isolation technology used in integrated circuits involves the process of locally oxidizing silicon. Local oxidation of silicon, or LOCOS process, involves oxidizing field regions between device active regions. The oxide grown in field regions is termed field oxide. Field oxide is grown during the initial stages of integrated circuit fabrication before the gate conductor and source/drain regions are formed in active areas. By growing a thick field oxide in isolation (or field) regions pre-implanted with a channel-stop dopant, LOCOS processing serves to prevent the establishment of parasitic channels in the field regions.
While LOCOS has remained a popular isolation technology, there are several problems inherent to LOCOS. First, a growing field oxide extends entirely across the field region and laterally as a bird's-beak structure. In many instances, the bird's-beak structure can unacceptably encroach into the device active area. Second, the pre-implanted channel-stop dopant often redistributes during the high temperatures associated with field oxide growth. Redistribution of channel-stop dopant primarily affects the active area periphery causing problems known as narrow-width effects. Third, the thickness of field oxide causes large elevational disparities across the semiconductor topography between field and active regions. Topological disparities cause planarity problems which become severe as circuit critical dimensions shrink. Lastly, thermal oxide growth is significantly thinner in small field (i.e., field areas of small lateral dimension) regions relative to large field regions. In small field regions, a phenomenon known as field-oxide-thinning effect may therefore occur.
Many of the problems associated with LOCOS technology are alleviated by an isolation technique known as shallow trench isolation ("STI"). Despite advances made to decrease bird's-beak, channel-stop encroachment and non-planarity, it appears that LOCOS technology is still inadequate for deep submicron technologies. The shallow trench process, herein "trench process", is better suited for isolating densely spaced active devices having field regions less than, e.g., 3.0-5.0 .mu.m in the lateral dimension. Narrow width STIs may be used to isolate densely spaced devices and larger width STIs may be used to isolate devices that are spaced further apart.
The trench process involves the steps of etching a silicon substrate surface to a relatively shallow depth, e.g., between 0.2 to 0.5 microns, and then filling the shallow trench with a deposited dielectric (referred to henceforth as "trench dielectric"). Some trench processes include an interim step of growing oxide on the trench walls prior to filling the trench with the dielectric. The trench dielectric may comprise decomposed tetra-ethyl-ortho-silicate ("TEOS") deposited using a chemical-vapor deposition ("CVD") process. CVD may, for example, be performed at approximately 400-600.degree. C. in an atmospheric pressure or low pressure chamber.
An exemplary STI structure is shown in FIG. 1. Semiconductor substrate 10 is shown having STI-associated trenches 12 and 14 placed therein. Deposited trench dielectric 16 conforms to the contour of the underlying structure defined by shallow trenches 12 and 14. As a result, upper surface 18 of trench dielectric 16 is lower in the field regions above trench isolation areas compared to the active regions. Furthermore, upper surface 18 is lower over large-width shallow trench 12 compared to upper surface 18 over small-width shallow trench 14. Subsequent device formation requires a substantially planar semiconductor topography. The various depositions and patterning associated with device formation are more easily and more accurately accomplished on a pre-existing planar surface. Loss of planarity can impact manufacturing yield. Exemplary problems include poor adhesion to underlying materials, step coverage problems, and depth of focus problems. A polishing step is thus required, prior to any device formation, to planarize the upper surface of trench dielectric 18 and bring it to a level approximately equal to the level of the upper surface of the semiconductor substrate. However, applying the polishing step at this point in the process would result in upper surface 18 over large-width shallow trench 12 to be below upper surface 20 of semiconductor substrate 10. To avoid this, an additional masking and etching step is generally required.
Referring now to FIG. 2, photoresist layer 22 is deposited upon the semiconductor substrate and then patterned in such a way as to cover trench dielectric 16 over large-width shallow trench 12. The remaining exposed portion of trench dielectric 16 is then etched using an anisotropic plasma etch. Trench dielectric 16 is etched to a level approximately equal to or lower than the level of upper surface 18 of trench dielectric 16 above large-width shallow trench 12. Isolated protrusions 24 and 26 remain extending upwards from the remainder of upper surface 18. After the etch process, photoresist 22 is removed and a chemical-mechanical polish ("CMP") is applied to the wafer as shown in FIG. 3. A CMP process combines a mechanical polishing pad with chemical abrasion. Raised areas contact the polishing pad to a greater extent than recessed areas. As a result, elevated features, like protrusions 24 and 26, are removed faster without correspondingly thinning flat areas. CMP is typically a "dirty" procedure mainly due to the slurry particles used during the process. After the CMP process, upper surface 18 of trench dielectric 16 is substantially planar.
The additional masking and etching steps are costly and decrease overall throughput. Furthermore, these extra processing steps add unnecessary complexity to the process increasing the possibility of error and contamination. It would thus be desirable to derive an alternative process which eliminates the need for the additional masking and etching steps in order to achieve substantially global planarization.